| DESIGN FUNCTION AND QUANTITY | 1 GATE, ARRAY |
| FEATURES PROVIDED | HERMETICALLY SEALED AND BURN IN AND MONOLITHIC |
| INCLOSURE CONFIGURATION | PIN GRID ARRAY |
| INCLOSURE MATERIAL | CERAMIC |
| PART NAME ASSIGNED BY CONTROLLING AGENCY | ISERE CMOS I GATE ARRAY PERSONALITY TURBO PROCESSOR CHIP |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| OUTPUT LOGIC FORM | COMPLEMENTARY-METAL OXIDE-SEMICONDUCTOR LOGIC |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TERMINAL TYPE AND QUANTITY | 144 PIN |
| TEST DATA DOCUMENT | 96906-MIL-STD-883 STANDARD (INCLUDES INDUSTRY OR ASSOCIATION STANDARDS, INDIVIDUAL MANUFACTUREER STANDARDS, ETC.). |
| TIME RATING PER CHACTERISTIC | 2.50 NANOSECONDS MAXIMUM DELAY |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 7.0 VOLTS MAXIMUM POWER SOURCE |